Hardware assurance pulls from across the technical stack. The cohort is a mix of engineers, researchers, and PhD students with depth in one of these areas.
Silicon and firmware
Tamper-evident hardware, silicon-level attestation, and firmware that participates in verification protocols.
Backgrounds in RTL, ASIC, SoC, FPGA, or embedded systems.
Hardware security
Mechanisms that hold up under physical attack and adversarial probing.
Backgrounds in secure hardware, side-channel countermeasures, or tamper protection.
Cryptography and formal methods
Making proof-of-inference practical, formally verifying attestation protocols, building zero-knowledge tooling.
Backgrounds in applied cryptography, zero-knowledge proof systems, or formal methods.
Trusted execution
Designing how labs and chips can prove what they’re running to a third party.
Backgrounds in TEEs, attestation, secure boot, or root-of-trust systems.
ML systems
Figuring out what’s actually verifiable in real ML workloads, and how.
Backgrounds in distributed training (NCCL, Megatron, DeepSpeed) or large-scale inference.
Networking
Network-level instrumentation that detects training-scale workloads from outside the rack.
Backgrounds in high-performance networking, line-rate packet processing, or deep packet inspection.
